1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to field effect transistors and manufacturing techniques on the basis of stressed dielectric layers formed above the transistors used for generating strain in channel regions of the transistors.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, may be a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance, by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One efficient approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting ing the stress characteristics of a dielectric layer stack that is formed above the basic transistor structure. The dielectric layer stack typically comprises one or more dielectric layers which may be located close to the transistor and which may also be used in controlling a respective etch process in order to form contact openings to the gate and drain and source terminals. Therefore, an effective control of mechanical stress in the channel regions, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress of these layers, which may also be referred to as contact etch stop layers, and by positioning a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas flow rates and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
During the formation of the two types of stressed layers, conventional techniques may suffer from reduced efficiency and increased yield loss when device dimensions are increasingly scaled by using the 90 nm technology and even further advanced approaches, due to the limited conformal deposition capabilities of the deposition process involved, which may result in respective process non-uniformities during subsequent process steps for patterning the stressed layer and forming contact openings, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a certain manufacturing stage for forming stress-inducing layers above a first device area 120A and a second device area 120B. The first and second device areas 120A, 120B, which typically represent respective transistor elements, may be formed above a substrate 101 comprising a semiconductor layer 102, such as a silicon-based layer, which may be separated from the substrate 101 by an appropriate buried insulating layer if a silicon-on-insulator (SOI) configuration is considered. In the example shown, the first and second device areas 120A, 120B may comprise a plurality of transistor elements with a lateral distance according to the design rules of the technology under consideration. The transistors in the first and second device areas 120A, 120B may comprise a gate electrode 121 formed on a respective gate insulation layer, which separates the gate electrode 121 from a corresponding channel region 124, which is laterally located between respective drain/source regions 125. Furthermore, a sidewall spacer structure 122 may be formed on sidewalls of the gate electrode 121. Typically, metal silicide regions (not shown) may be provided in the drain and source regions 125 and the gate electrodes 121 in order to enhance the conductivity of these areas. The semiconductor device 100 may represent an advanced device in which critical dimensions, such as the gate length, i.e., in FIG. 1a, the horizontal extension of the gate electrodes 121, may be approximately 50 nm or significantly less. Consequently, a distance between respective transistor elements, i.e., the lateral distance between neighboring sidewall spacer structures 122 of closely spaced transistor elements, may be approximately 100 nm or even less, wherein, depending on the device configuration, in dense device areas, a plurality of closely spaced circuit elements may be provided.
It should be appreciated that the first and second device regions 120A, 120B may be separated by an appropriate isolation structure (not shown) if required. Furthermore, in the manufacturing stage shown in FIG. 1a, a silicon nitride layer 130 comprising a high intrinsic stress may be formed above the first and second device areas 120A, 120B followed by an etch indicator layer 131 comprised of silicon dioxide. It should be appreciated that, if required, an etch stop layer, such as a silicon dioxide layer of appropriate thickness and density, may be provided between the silicon nitride layer 130 and the respective transistor elements in the first and second device areas 120A, 120B.
As is evident from FIG. 1a, due to the reduced spacing between neighboring transistor elements, the silicon nitride layer 130 may define a respective surface topography in which tapered recesses, also referred to as seams 132, may be formed between the closely spaced transistor elements, since the spacing between the transistor elements may be in the order of two times a layer thickness of the silicon nitride layer 130, which, in combination with the limited conformal fill behavior, may even result in corresponding defects, such as voids 132A and the like.
Furthermore, in this manufacturing stage, the semiconductor device 100 may comprise a resist mask 103 exposing the first device area 120A while covering the second device region 120B. In this case, it may be assumed that the intrinsic stress of the silicon nitride layer 130 may be appropriately selected so as to enhance the transistor performance in the second device area 120B, which may, for instance, include N-channel transistors requiring a high tensile stress in the layer 130.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. The gate electrodes 121 and the gate insulation layers may be formed and patterned on the basis of well-established process techniques including advanced photolithography, deposition, oxidation and etch techniques. Thereafter, the drain and source regions 125 may be formed in combination with the sidewall spacer structures 122 on the basis of well-established deposition processes, anisotropic etch processes and implantation sequences in order to establish the desired vertical and lateral dopant profile. Thereafter, respective silicide regions may be formed, if required, on the basis of well-established techniques. Next, if required, a corresponding silicon dioxide etch stop layer may be formed followed by the deposition of the silicon nitride layer 130. During the deposition of the silicon nitride material, respective process parameters, such as composition of carrier gases and reactive gases, substrate temperature, deposition pressure and, in particular, ion bombardment during the deposition, may significantly influence the finally obtained intrinsic stress of the material as deposited with respect to the underlying materials. For example, when the layer 130 is deposited with high tensile stress of up to 1 GPa or even significantly higher, the ion bombardment is reduced, for instance, by establishing the deposition atmosphere with a low level of radio frequency (RF) power so as to obtain the desired tensile property of the material as deposited. However, the moderately low RF power may result in reduced surface diffusion of the reactive species in the deposition ambient, thereby compromising conformality. Due to the less pronounced conformality of the silicon nitride deposition process above a certain layer thickness and for increased aspect ratios, as may occur in highly scaled devices, caused by the reduced distance between the neighboring transistor elements at moderately dimensioned gate heights in densely packed device areas, as shown, the silicon nitride material may merge in the lateral growth direction between closely spaced transistor elements, thereby forming the respective seam 132, or respective overhangs may form, thereby resulting in the void 132A. Thus, in the subsequent deposition of the silicon dioxide layer 131, the local deposition conditions at the seam 132 may result in a non-uniformity of the layer thickness, thereby giving rise to respective etch non-uniformities in a contact etch process to be performed in a later stage.
After the deposition of the silicon dioxide layer 131, the resist mask 103 may be formed on the basis of well-established photolithography techniques. Next, an appropriately designed etch process may be performed in order to remove a portion of the layers 130 and 131 from the first device area 120A. During the corresponding etch process, the silicon dioxide material of the layer 131 may be removed first followed by a selective etch process for removing the material of the silicon nitride layer 130, wherein the corresponding etch process may be controlled on the basis of an etch stop layer, if required. Due to the significantly increased layer thickness of the silicon dioxide layer 131 at the seam 132, the material may not be completely removed during the etch process when removing the layer 131, thereby significantly blocking the selective etch chemistry during the subsequent etch process for removing the exposed portion of the silicon nitride layer 130.
Consequently, respective material residuals may remain between the transistors in the first device area 120A, which may result in respective non-uniformities during the further processing, for instance, during the deposition of a further dielectric layer of high intrinsic stress designed to enhance the transistor performance of the transistors in the first device area 120A.
FIG. 1b schematically illustrates the semiconductor device 100 at a further advanced manufacturing stage. As shown, a second dielectric layer 140, for instance having a compressive stress, may be formed above the first and second device areas 120A, 120B. Consequently, due to the material residual 132 previously produced during the removal of the tensile layer 130, the respective stress transfer mechanism may be deteriorated, while additionally the residual 132 may provide respective etch non-uniformities in the subsequent patterning sequence for forming respective contact openings. Similarly, the void 132A in the second device region 120B may also result in a reduced stress transfer mechanism, as well as degraded etch uniformity during the subsequent processing.
As a consequence, upon further device scaling, the respective limitation of deposition processes for dielectric materials of high intrinsic stress, in particular for tensile-stressed silicon nitride, may require a significant reduction of the layer thickness to comply with increased aspect ratios encountered in advanced device geometries. However, in this case, the respective strain induced by the stressed dielectric materials may also be significantly reduced, thereby also reducing transistor performance, in particular performance of N-channel transistors.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.